1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular, to a semiconductor device which is suited to an SOI structure and a method of manufacturing the same.
2. Description of the Related Art
One technique of manufacturing a semiconductor is the SOI (Semiconductor-On-Insulator) technique which is as follows. An insulating film (such as a silicon oxide film) which serves as a buffer layer is grown on an insulating substrate of silicon oxide or sapphire or the like. Thereafter, a semiconductor thin film is formed on the insulating film. For example, a unipolar transistor element such as a MOS transistor, or a bipolar transistor element is built-in in this semiconductor thin film. In a semiconductor device such as a semiconductor integrated circuit (IC) having an SOI structure formed by this SOI technique, the junction capacitance is lower than that of a semiconductor device formed at a bulk semiconductor. Thus, a semiconductor device having an SOI structure has advantages such as the operational speed of the semiconductor device is improved.
In such an IC, generally, a large number of the same IC portions are formed collectively on a substrate wafer. Pads, which are the connection terminals to the respective internal circuits, are formed on the surface of the substrate wafer for the respective IC portions. The IC portions of the substrate wafer are cut out and separated as chips by, for example, cleavage using scribe lines. In this way, the individual IC chips are formed.
The IC chips are packaged in order to facilitate handling thereof at the time the IC chip is assembled with a circuit board or the like. In a chip scale package (CSP), a package plate is used which is formed from an insulating plate made of, for example, polyimide, at which connection terminals corresponding to the respective pads are provided. In a CSP, before the wafer is separated into the IC chips, the surfaces of the IC chips are covered by the package plate so that the pads for the internal circuits provided at the wafer surface abut the connection terminals corresponding to the package plate.
Potential is applied to the IC substrate in order to ensure stable operation of the IC chip. In order to apply potential to the IC substrate, the following has been proposed. Pads for electrical connection to the IC substrate are provided on the IC chip surface opposing the package plate. (Hereinafter, these pads will be referred to as xe2x80x9cpads for the substratexe2x80x9d.) Embedded plug portions, which extend from the pads through the interior of the IC chip toward the substrate, are formed.
In this way, conductive portions, which extend from the IC substrate to the pads for the substrate provided at the IC surface, are formed as embedded plug portions which extend through the interior of the IC chip. Thus, potential can be applied to the IC substrate from the IC chip surface which is at the same side at which the package plate is positioned and other pads for the internal circuit are provided, without leading to a substantial increase in the surface area required for the IC chip, i.e., without making the IC chip less compact.
However, in the above-described conventional structure, a special additional processing is required in order to form, by etching and within the main body of the IC chip, the holes for forming the embedded plug portions. Thus, manufacturing becomes complex. Further, the surface area of contact between the substrate and the embedded plug portion, which is embedded in the hole formed by etching, is determined by the hole diameter of the etched hole and the like, and is relatively small. Thus, the conventional structure is not preferable from the standpoint of reliable and stable application of potential.
In addition, the conventional structure affects the chip layout as well, and results in the semiconductor device being less compact.
An object of the present invention is to provide a semiconductor device which can be manufactured relatively easily and can ensure a stable substrate potential without a loss of compactness of the semiconductor device, and to provide a method of manufacturing the semiconductor device.
In order to achieve the above object, cut grooves are utilized in the present invention. The cut grooves are formed in a substrate wafer, at which semiconductor devices are collectively formed, for separating the substrate wafer into semiconductor chips of the respective semiconductor devices. A conductive layer, which extends to electrode pads for electrical connection to the substrate, is formed in the groove surface of the cut groove.
Namely, a method of manufacturing a semiconductor device according to the present invention includes the steps of: forming cut grooves in a wafer which becomes a substrate, the wafer including a semiconductor layer which is disposed on the wafer via an insulating layer and at which a plurality of same semiconductor circuits are formed collectively, a surface oxide film which covers the semiconductor layer, and electrode pads for electrical contact with the substrate, the electrode pads being formed on the surface oxide film in correspondence with the respective semiconductor circuits, the cut grooves being formed in the wafer from the surface oxide film to the substrate, for separating the wafer into chips of the respective semiconductor circuits; and before separating the wafer into the chips, forming a conductive layer on groove surfaces of the cut grooves, the conductive layer extending from a substrate region via the groove surfaces of the cut grooves to the electrode pads.
In accordance with the method relating to the present invention, the conductive layer, which connects the chip substrate positioned at the reverse surface side of the chip and the electrode pads for the substrate which are positioned at the front surface side of the chip, is not provided within the chip. There is no need to subject the inner portion of the chip to etching in order to form the conductive layer.
The conductive layer is formed at the groove surfaces of the cut grooves by using the cut grooves which are provided in order to separate the chips. Thus, no bonding wire projects outwardly of the IC chip to a great extent, as in the case in which bonding wires are used, and therefore, the dimensions of the IC chip do not substantially increase. Accordingly, the IC chip can be made compact.
Further, the conductive layer which connects the substrate and the electrode pads for the substrate is connected to the substrate at the peripheral side surface of the substrate. Therefore, as compared to a conventional method using embedded plug portions, the electrode pads can be connected to the substrate over a wider connection surface area. Thus, a desired potential can be stably and reliably applied to the substrate.
The cut grooves may be grid lines disposed in a lattice configuration on the substrate wafer for separating the wafer into the respective chips. Further, the conductive layer may be formed by heating after a paste-like conductive material which hardens by heating, e.g., solder paste or silver paste, is applied to predetermined places including the groove surfaces of the cut grooves.
In the method of manufacturing a semiconductor device according to the present invention, preferably, the wafer is formed from silicon oxide, and the silicon oxide, together with the insulating layer and the semiconductor layer, forms an SOI structure. Namely, the method of the present invention is suitable for manufacturing SOI devices. However, instead, the present invention may be applied to a CMOS-LSI having a wafer portion which is electrically isolated from the substrate via an insulating layer. Or, the present invention may be applied to an LSI which is electrically isolated from the substrate by a dielectric.
The semiconductor device relating to the present invention includes a substrate; a semiconductor layer which is disposed on said substrate via an insulating layer, and in which a semiconductor circuit is built in; a surface oxide film covering said semiconductor layer; an electrode pad which is provided on said surface oxide film and which is for electrical contact with said substrate; and a conductive layer for electrically connecting said electrode pad and said substrate, wherein said conductive layer surrounds peripheral surfaces of said semiconductor device including side surfaces of said substrate, and surrounds edge portions of said surface oxide film.
The conductive layer is formed so as to surround the side surfaces of the substrate. Thus, in order to connect the electrode pads and the substrate, there is no need to use a bonding wire which protrudes out to a great extent at the outer side of the semiconductor device, and there is no need for conventional conductive plugs which extend through the interior of the IC chip. Due to the conductive layer, the substrate and the electrode pads formed on the surface oxide film covering the substrate can be suitably connected together.
The conductive layer does not have to be formed continuously along the peripheral direction at the peripheral surfaces of the substrate, and may be formed intermittently along the peripheral direction of the substrate. In this way, portions of the side surfaces of the substrate along the peripheral direction thereof can be exposed from the conductive layer. However, in order to achieve more reliable electrical contact and to also protect the chip by the conductive layer, it is preferable that the conductive layer be formed continuously along the peripheral direction of the semiconductor device at the entire region of the side surfaces of the substrate and at the edge portions of the surface oxide film.